Basic I2C Data Transfer
This section describes the basic method of transferring data via I2C. Assuming the receiver and transmitter are in sync, data bits are transferred much like an RS232 serial port, only without the start and stop bits. This data transfer method is used when broadcasting the Slave address, and for transfering actual data.
In the figure at the right, this diagram shows the clock line (SCL) running at a non-constant frequency. This is on purpose, as it demonstrates that I2C can handle software-generated clock signals, which may not be regular.
This waveform diagram shows a hex 0x13 (Binary 00010011) getting transferred over I2C. The low-to-high transitions on the SCL clock line indicate where the data line (SDA) is sampled. The bits come in with the most-significant bit (MSB) first. An additional rule is that under normal data transfer, the data line must remain stable while SCL is high. The device which is driving the SDA data line must wait until the clock line goes low before changing the state. There is an exception to that rule for the START and STOP conditions.
How the Master Addresses the Slave
Remember that I2C busses can contain up to 127 devices. The Master must specify which device it wants to read or write from before any data can be transferred. The Master does this by sending a byte with a device address after causing the START condition. The device addresses are assigned by the circuit designer, who reads the datasheets for each I2C part on the bus, and then ensures that the devices have non-conflicting addresses.
Immediately following the START condition, the master sends an 8-bit data byte onto the bus. The slave's address is the first 7 bits, followed by a one-bit read/write code. A '0' bit in the LSB of the address indicates the master is starting a write transaction. A '1' bit in the LSB indicates a read transaction. Once the SCL line comes low again after the last of the addr+r/w byte, the master releases the SDA line so it floats high. At this time, the slave device should have recognized its address and should acknowledge (ACK) the transaction by pulling the SDA line low. This is how the Master will know if the Slave is listening.
In the diagram, the bus is initially idle, with both SCL and SDA high. Then the Master signals a START condition by bringing SDA low. After this, the MASTER clocks out 8 bits on the SDA line. The first 7 bits forms the Slave address. The last bit is a '0' if the Master wants to write to the Slave, or a '1' if the Master wants to read from the Slave.
After the Master has shifted out that RD/WRT bit, it then lets go of the SDA line. (After SCL goes low, of course) Now if a slave has recognized its address, it should pull the SDA line low. On the next low-to-high transition of SCL, the Master examines the SDA line. If is low, that means a Slave has Acknowledged, and the transaction may continue. (The Slave must hold the SDA low for as long as SCL remains high.)
If the SDA line is high, then no Slave device responded, and the transaction should be aborted.
Writing the Data to the Slave
If a Slave device ACK'd the address put out by the MASTER in the previous 8 clocks, then the Master will begin the write or read operation.
In this figure, the first three clock cycles are copied from the previous figure. Once the address ACK cycle is over, the Master then starts clocking data into the slave. On every rising SCL edge, the slave is shifting in bits of the data word.
After 8 bits, the slave should have the entire byte, and then the data must ACK'd. This should proceed just like the ACK for the address. The Master releases the SDA line, and the Slave pulls it low and holds it as long as SCL is high. As soon as SCL comes back down, the Slave must release the SDA line so that the bus is idle, and the Master can clock in another byte, or issue a STOP and/or a START condition to begin another transaction.
Reading Data From the Slave
Reading data from the Slave is almost identical to the write, except that after the address ACK, the slave will be driving SDA line. In addition, now the ACK will actually be generated by the Master. After 8 clocks of a data, the Master can bring the SDA line low if another byte is desired, or it can leave the SDA line high. If the Master does NOT ack the byte, it indicates the transaction is over.
For more In-Depth Information See NXP's Official I2C Documentation
How to Write I2C Code for your Microcontroller
Want to use I2c on your own cpu? See this article for some easy to adapt source code with comments.